View MB82D01181E-60LPBN_1768389.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds05-11424-4e fujitsu semiconductor data sheet copyright?2004-2006 fujitsu limited all rights reserved memory mobile fcram tm cmos 16 mbit (1 m word 16 bit) mobile phone application specific memory mb82d01181e -60l description mb82d01181e is a fast cycle random access memo ry (fcram) with asynchronous static random access memory (sram) interface containing 16,777,216 storages accessible in a 16-bit format. mb82d01181e is suited for mobile applications such as cellular handset and pda. note: fcram is a trademark of fujitsu limited, japan. features ? asynchronous sram interface 1 m word 16 bit organization low-voltage operating conditions : v dd = 2.3 v to 3.5 v wide operating temperature : t a = 0 c to + 70 c read/write cycle time : t rc = t wc = 70 ns min fast random access time : t aa = t ce = 60 ns max active current : i dda1 = 20 ma max standby current : i dds1 = 100 a max (v dd 3.1 v) power down current : i ddp = 10 a max byte control shipping form : wafer/chip, 48-pin plastic fbga
mb82d01181e -60l 2 pin assignment pin description pin name description a 19 to a 0 address input ce 1 chip enable (low active) ce2 chip enable (high active) we write enable (low active) oe output enable (low active) lb lower byte control (low active) ub upper byte control (low active) dq 8 to dq 1 lower byte data input/output dq 16 to dq 9 upper byte data input/output v dd power supply v ss ground nc no connection a b c d e f g h lb dq 9 dq 10 v ss v dd dq 15 dq 16 a 18 oe ub dq 11 dq 12 dq 13 dq 14 a 19 a 8 a 0 a 3 a 5 a 17 nc a 14 a 12 a 9 a 1 a 4 a 6 a 7 a 16 a 15 a 13 a 10 a 2 ce1 dq 2 dq 4 dq 5 dq 6 we a 11 ce2 dq 1 dq 3 v dd v ss dq 7 dq 8 nc 16 5 4 3 2 (top view) (bga-48p-m18) sram compatible fbga (suffix pbn)
mb82d01181e -60l 3 block diagram v dd v ss ce2 ce1 we lb ub oe a 19 to a 0 d q 8 to dq 1 d q 16 to dq 9 address latch & buffer row decoder memory cell array 16,777,216 bits i/o buffer input data latch & control sense / switch output data control column decoder address latch & buffer power control timing control
mb82d01181e -60l 4 function truth table note : l = v il , h = v ih , x = either v il or v ih , high-z = high impedance *1 : output disable mode should not be kept longer than 1 s. *2 : power down mode can be enter ed from standby state and all dq pins are in high-z state. *3 : can be either v il or v ih but must be valid before read or write. mode ce2 ce 1we oe lb ub a 19 to a 0 dq 8 to dq 1 dq 16 to dq 9 i dd data retention standby (deselect) h h x x x x x high-z high-z i dds yes output disable* 1 l h h x x *3 high-z high-z i dda no read hl h h valid high-z high-z read (upper byte) h l valid high-z output valid read (lower byte) l h valid output valid high-z read (word) l l valid output valid output valid no write lh h h valid invalid invalid write (upper byte) h l valid invalid input valid write (lower byte) l h valid input valid invalid write (word) l l valid input valid input valid power down * 2 l x x x x x x high-z high-z i ddp no
mb82d01181e -60l 5 absolute maximum ratings * : all voltages are referenced to v ss . warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions *1 : all voltages are referenced to v ss . *2 : this device supports three voltage ranges, v dd (31) , v dd (27) , and v dd (23) on identical device. v dd range is divided into three ranges on the table due to v ih varied according to v dd supply voltage. *3 : overshoot spec. (v ih (max) = v dd + 1.0 v, pulse width 5.0 ns) *4 : undershoot spec. (v il (min) = ? 1.0 v, pulse width 5.0 ns) warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max supply voltage * v dd ? 0.5 + 3.6 v input voltage * v in ? 0.5 + 3.6 v output voltage * v out ? 0.5 + 3.6 v short circuit output current i out ? 50 + 50 ma storage temperature t stg ? 55 + 125 c parameter symbol value unit min max supply voltage * 1, * 2 v dd (31) 3.1 3.5 v v dd (27) 2.7 3.1 v v dd (23) 2.3 2.7 v v ss 00v high level input voltage * 1, * 2, * 3 v ih (31) v dd 0.8 v dd + 0.2 and 3.5 v v ih (23, 27) v dd 0.8 v dd + 0.2 v low level input voltage * 1, * 4 v il ? 0.3 v dd 0.2 v ambient temperature t a 0 + 70 c
mb82d01181e -60l 6 pin capacitance (f = 1.0 mhz, t a = + 25 c) dc characteristics notes: ? all voltages are referenced to vss. ? dc characteristics are measured after following power-up timing. ? i out depends on the output load conditions. parameter symbol conditions value unit min typ max address input capacitance c in1 v in = 0 v ?? 5pf control input capacitance c in2 v in = 0 v ?? 5pf data input/output capacitance c io v io = 0 v ?? 8pf parameter symbol conditions value unit min max input leakage current i li v ss v in v dd ? 1.0 + 1.0 a output leakage current i lo v ss v out v dd , output disable ? 1.0 + 1.0 a output high voltage level v oh(31) v dd = v dd(31) min, i oh = ? 0.5 ma 2.5 ? v v oh(27) v dd = v dd(27) min, i oh = ? 0.5 ma 2.2 ? v v oh(23) v dd = v dd(23) min, i oh = ? 0.5 ma 1.8 ? v output low voltage level v ol i ol = 1 ma ? 0.4 v v dd power down current i ddp v dd = v dd max, v in = v ih or v il , ce2 0.2 v ? 10 a v dd standby current i dds v dd = v dd(31) max, v in = v ih or v il , ce 1 = ce2 = v ih ? 2.0 ma v dd = v dd(27 , 23) max, v in = v ih or v il , ce 1 = ce2 = v ih ? 1.0 i dds1 v dd = v dd(31) max, v in 0.2 v or v in v dd ? 0.2 v, ce 1 = ce2 v dd ? 0.2 v ? 150 a v dd = v dd(27 , 23) max, v in 0.2 v or v in v dd ? 0.2 v, ce 1 = ce2 v dd ? 0.2 v ? 100 v dd active current i dda1 v dd = v dd max, v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma t rc / t wc = min ? 20 ma t rc / t wc = 1 s ? 3.0
mb82d01181e -60l 7 ac characteristics (1) read operation *1 : maximum value is applicable if ce 1 is kept at low without any address change. *2 : address should not be changed within minimum t rc . *3 : the output lo ad 50 pf with 50 ? termination to v dd 0.5 v. *4 : the output load 5 pf without any other load. *5 : applicable when ce 1 is kept at low. *6 : t rc (min) must be satisfied. *7 : if the actual value of t whol is shorter than specified minimum value, the actual t aa of following read may become longer by the amount of subtracting act ual value from specified minimum value. parameter symbol value unit notes min max read cycle time t rc 70 1000 ns *1, *2 ce 1 access time t ce ? 60 ns *3 oe access time t oe ? 40 ns *3 address access time t aa ? 60 ns *3, *5 lb , ub access time t ba ? 30 ns *3 output data hold time t oh 5 ? ns *3 ce 1 low to output low-z t clz 5 ? ns *4 oe low to output low-z t olz 0 ? ns *4 lb , ub low to output low-z t blz 0 ? ns *4 ce 1 high to output high-z t chz ? 20 ns *3 oe high to output high-z t ohz ? 20 ns *3 lb , ub high to output low-z t bhz ? 20 ns *3 address setup time to ce 1 low t asc ? 5 ? ns address setup time to oe low t aso 10 ? ns address invalid time t ax ? 10 ns *5 address hold time from ce 1 high t chah ? 5 ? ns *6 address hold time from oe high t ohah ? 5 ? ns we high to oe low time for read t whol 10 1000 ns *7 ce 1 high pulse width t cp 10 ? ns
mb82d01181e -60l 8 (2) write operation *1 : maximum value is applicable if ce 1 is kept at low without any address change. *2 : minimum value must be equal or greater than the sum of write pulse width (t cw , t wp or t bw ) and write recovery time (t wr ) . *3 : write pulse width is defined from high to low transition of ce 1, we , lb or ub , whichever occurs last. *4 : applicable for byte mask only. byte mask setup time is defined to the high to low transition of ce 1 or we whichever occurs last. *5 : applicable for byte mask only. byte mask hold time is defined from the low to high transition of ce 1 or we whichever occurs first. *6 : write recovery time is defined from low to high transition of ce 1, we , lb or ub , whichever occurs first. *7 : if oe is low after minimum t ohcl , read cycle is initiated. in other words, oe must be brought to high within 5 ns after ce 1 is brought to low. *8 : if oe is low after new address input, read cyc le is initiated. in other words, oe must be brought to high at the same time or before new address valid. note : ac characteristics are measured after following power-up timing. parameter symbol value unit notes min max write cycle time t wc 70 1000 ns *1, *2 address setup time t as 0 ? ns *2 ce 1 write pulse width t cw 45 ? ns *3 we write pulse width t wp 45 ? ns *3 lb , ub write pulse width t bw 45 ? ns *3 lb , ub byte mask setup time t bs ? 5 ? ns *4 lb , ub byte mask hold time t bh ? 5 ? ns *5 write recovery time t wr 0 ? ns *6 ce 1 high pulse width t cp 10 ? ns we high pulse width t whp 10 1000 ns lb , ub high pulse width t bhp 10 1000 ns data setup time t ds 15 ? ns data hold time t dh 0 ? ns oe high to address setup time for write t oes 0 ? ns *8 oe high to ce 1 low setup time for write t ohcl ? 5 ? ns *7 lb and ub write pulse overlap t bwo 30 ? ns
mb82d01181e -60l 9 (3) power down parameters * : applicable also to power-up. (4) other timing parameters *1: some data might be written into any address location if t chwx (min) is not satisfied. *2: the input transition time (t t ) at ac testing is 5 ns as shown in below. if actual t t is longer than 5 ns, it may violate ac specifications of some timing parameters. (5) ac test conditions (6) ac measurement output load circuit parameter symbol value unit note min max ce2 low setup time for power down entry t csp 10 ? ns ce2 low hold time after power down entry t c2lp 80 ? ns ce 1 high hold time following ce2 high after power down exit t chh 300 ? s* ce 1 high setup time following ce2 high after power down exit t chs 0 ? ns parameter symbol value unit note min max ce 1 high to oe invalid time for standby entry t chox 10 ? ns ce 1 high to we invalid time for standby entry t chwx 10 ? ns *1 ce2 low hold time after power-up t c2lh 50 ? s ce 1 high hold time following ce2 high after power-up t chh 300 ? s input transition time t t 125ns*2 parameter symbol conditions measured value unit note input high level v ih ? v dd 0.8 v input low level v il ? v dd 0.2 v input timing measurement level v ref ? v dd 0.5 v input transition time t t between v il and v ih 5ns 50 50 pf v dd 0.1 f v ss v dd 0.5 v device under test out
mb82d01181e -60l 10 timing diagram 1. read timing 1 (basic timing) 2. read timing 2 (oe & address access) t chah t asc t cp ce1 dq t chz t ohz t bhz t oh t rc t ce t oe t asc t ba t blz t olz t clz oe lb, ub address address valid valid data output (output) note : this timing diagram assumes ce2 = ?h? and we = ?h?. t aa t ohah dq t ohz t oh t rc t aa t oe t aso t olz ce1 oe lb, ub low t rc t ax t oh note : this timing diagram assumes ce2 = ?h? and we = ?h?. address address valid valid data output (output) address valid valid data output
mb82d01181e -60l 11 3. read timing 3 (lb , ub byte access) 4. write timing 1 (basic timing) t ax dq 8 to dq 1 t oh t rc t aa t ba t blz ce1 oe lb low t ax t oh t bhz t bhz t oh t blz t blz t ba t ba t bhz , ub d q 16 to dq 9 address address valid valid data output (output) valid data output valid data output (output) note : this timing diagram assumes ce2 = ?h? and we = ?h?. t wr t cp ce1 t ohcl t wr t bhp t dh t wc t cw t wp t as t bw we lb, ub t as t as t as t as t as t ds t wr t whp oe dq address address valid valid data input (input) note : this timing diagram assumes ce2 = ?h?.
mb82d01181e -60l 12 5. write timing 2 (we control) 6. write timing 3-1 (we , lb , ub byte write control) ce1 t oes t wp t dh t wr t ohah t whp we l b, ub t as t wp t wr t ds oe dq low t wc t as t wc t ohz t dh t ds address address valid (input) valid data input valid data input address valid note : this timing diagram assumes ce2 = ?h?. t bs t wp t dh t wr t whp ce1 we lb t as t wp t wr t ds dq 8 to dq 1 low t wc t as t wc t dh t ds t bh t bh t bs ub d q 16 to dq 9 address address valid (input) valid data input valid data input (input) address valid note : this timing diagram assumes ce2 = ?h? and oe = ?h?.
mb82d01181e -60l 13 7. write timing 3-2 (we , lb , ub byte write control) 8. write timing 3-3 (we , lb , ub byte write control) t bs t wr t dh t wr t whp ce1 we lb t bw t as t ds dq 8 to dq 1 low t wc t as t wc t dh t ds t bh t bh t bs ub dq 16 to dq 9 t bw address address valid (input) valid data input valid data input (input) address valid note : this timing diagram assumes ce2 = ?h? and oe = ?h?. ce1 t bs t dh t wr t whp we lb t as t bw t ds ub dq 8 to dq 1 low t wc t wc t bh t dh t ds t as t bw t wr t bs t bh dq 16 to dq 9 address address valid (input) valid data input valid data input (input) address valid note : this timing diagram assumes ce2 = ?h? and oe = ?h?.
mb82d01181e -60l 14 9. write timing 3-4 (we , lb , ub byte write control) 10. read/write timing 1-1 (ce 1 control) t bw t dh t wr t as ce1 we lb t as t bw ub dq 8 to dq 1 low t wc t wc t bhp t dh t ds t as t bw t wr dq 16 to dq 9 t dh t ds t dh t ds t bw t bwo t bhp t wr t bwo t wr t as t ds address address valid (input) valid data input valid data input (input) address valid valid data input valid data input note : this timing diagram assumes ce2 = ?h? and oe = ?h?. t ohcl t cp t wr t chah ce1 we t as t cw ub, lb dq t wc t rc t ce t asc t dh t ds t chah t oh t chz t oh t cp oe t clz note : this timing diagram assumes ce2 = ?h?. write address is valid from either ce 1 or we of last falling edge. address write address write data input read address read data output read data output
mb82d01181e -60l 15 11. read/write timing 1-2 (ce 1, we , oe control) 12. read/write timing 2 (oe , we control) t ohcl t cp t wr t chah ce1 we t as t wp ub, lb dq t wc t rc t ce t asc t dh t ds t oe t chah t oh t chz t oh t cp oe t olz note : this timing diagram assumes ce2 = ?h?. oe can be fixed low during write operation if it is ce 1 controlled write at read-write-read sequence. address write address write data input read address read data output read data output low t oes t wr t ohah ce1 we t as t wp ub, lb dq t wc t rc t aa t ohz t ds t oe t ohah t oh t ohz t oh oe t olz t aso t dh t whol address write address write data input read address read data output read data output note : this timing diagram assumes ce2 = ?h?. ce 1 can be tied to low for we and oe controlled operation.
mb82d01181e -60l 16 13. read/write timing 3 (oe , we , lb , ub control) low t oes t wr t ohah ce1 we t as t bw ub, lb dq t wc t rc t aa t bhz t ds t ohah t oh t bhz t oh oe t blz t aso t dh t whol t ba address write address write data input read address read data output read data output note : this timing diagram assumes ce2 = ?h?. ce 1 can be tied to low for we and oe controlled operation.
mb82d01181e -60l 17 14. power-up timing 1 15. power-up timing 2 ce1 ce2 t chh v dd t chs t c2lh v dd (min) 0 v note : t c2lh specifies after v dd reaches specified minimum level. ce1 ce2 t chh v dd v dd (min) 0 v note : t chh specifies after v dd reaches specified minimum level and applicable to both ce 1 and ce2. if transition time of v dd (from 0 v to v dd min) is longer than 100 ms, power-up timing#1 must be applied.
mb82d01181e -60l 18 16. power down entry and exit timing 17. standby entry timing after read or write t chs t chh t c2lp t csp power down entry power down mode power down exit high-z c e1 c e2 dq note : this power down mode can be also used as a reset timing if powe r-up timing could not be satisfied. t chox t chwx c e1 oe we active (read) standby active (write) standby note : both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce 1 low to high transition.
mb82d01181e -60l 19 bonding pad information please contact local fujitsu representative for pad layout and pad coordinate information. ordering information part no. shipping form/package remarks mb82d01181e-60lwt wafer MB82D01181E-60LPBN 48-pin plastic fbga (bga-48p-m18) sram compatible fbga package t ce = 60 ns max
mb82d01181e -60l 20 package dimension 4 8 -pin pla s tic fbga ball pitch 0.75 mm package width package length 6.00 9.00 mm lead s hape fine pitch ball s ealing method pla s tic mold mounting height 1.20 mm max weight 0.10 g 4 8 -pin pla s tic fbga (bga-4 8 p-m1 8 ) (bga-4 8 p-m1 8 ) c 2001 fujit s u limited b4 8 01 8s -c-1-1 9.00 0.10(.354 .004) 6.00 0.10 (.236 .004) 0.25 0.10 (.010 .004) .041 ? .004 +.006 ? 0.10 +0.15 1.05 index area (mounting height) ( s tand off) 0.10(.004) 0.20(.00 8 ) s s (5.25(.207)) (3.75(.14 8 )) 0.75(.030) typ 0.75(.030) typ 6 5 4 3 2 1 h g fedcb 4 8 -?0.35 0.10 (4 8 -?.014 .004) m 0.0 8 (.003) s a index mark dimen s ion s in mm (inche s ). note: the value s in parenthe s e s are reference value s .
mb82d01181e -60l f0607 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. edited business promotion dept.

▲Up To Search▲

Price & Availability of MB82D01181E-60LPBN

	To Download MB82D01181E-60LPBN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .